A common challenge confronted in the design of high performance, microprocessor-based devices is the reduction and control of electromagnetic interference (xe2x80x9cEMIxe2x80x9d) generated and/or radiated from such devices. Products, such as computers, having excessive EMI emissions may adversely affect the performance and operation of other electronic products situated close by. Therefore, many governmental agencies, including the FCC in the United States, have established limits on EMI emissions by products incorporating such devices. Specifically, FCC regulations specify how much electromagnetic energy a product may radiate at any particular frequency.
U.S. Pat. Nos. 5,488,627, 5,631,920, 5,867,524 and 5,872,807 provide spread spectrum clock generator (xe2x80x9cSSCGxe2x80x9d) circuit modules designed to reduce the EMI emissions in an electronic device by conditioning the clock signals driving microprocessor-based components (or other specialized circuits) in the electronic device. These modules frequency modulate an externally generated clock signal (such as a signal generated by a piezoelectric crystal driven at its resonant frequency by a suitable driver or oscillator circuit) to provide a spread spectrum output clock signal, which is used to drive the microprocessor-based components (or other specialized circuits) in the electronic device. The frequency modulation of the clock signal reduces spectral amplitude of the EMI components at each harmonic of the clock when compared to the spectrum of the same clock signal without modulation.
It is common for electronic components, such as printers, fax machines, scanners, etc., to utilize at least one application-specific integrated circuit (xe2x80x9cASICxe2x80x9d) device in place of, or in addition to, microprocessor-based circuits. ASIC devices are advantageous for many reasons. For example, since ASIC devices do not rely upon the use of software to control the functions of a microprocessor, the ASIC devices are typically more robust. Additionally, since ASIC devices are usually designed for a specific application, they can be designed to operate faster and can be less expensive than microprocessor-based circuits. Of course, the expense of the ASIC device, and in-turn, the electronic component utilizing the ASIC device, is dependent upon the number of pins and silicon area necessary for the ASIC device.
Due to the EMI concerns discussed above, it may be advantageous to design certain ASIC devices to incorporate SSCG modules in their architecture. One possible disadvantage with this architecture is that some internal or external components, such as USB (universal serial bus) modules, operatively coupled to, or part of the electronic device are not compatible with the frequency modulated clock output of the SSCG modules; and hence, certain sections of the ASIC that are designed to control or be operatively coupled to such external components may need to be designed to operate with and provide clock signals that are not frequency modulated (xe2x80x9cpurexe2x80x9d clock signals). If separate clock sources are utilized by the ASIC, however, there may arise synchronization problems and drift/skew/delay errors in the clock I/O buffers, between the various sections of the ASIC and/or between the various components coupled to, or part of the electronic device.
Therefore, there is a need for an ASIC architecture that incorporates an SSCG module therein and that utilizes and/or provides both a frequency modulated clock signal and an unmodulated clock signal, where the frequency modulated clock signal and the unmodulated clock signal are synchronized and where the ASIC architecture minimizes the number of pins and silicon area needed for the ASIC device.
The present invention provides an ASIC architecture that incorporates an SSCG module therein and that utilizes both a frequency modulated clock signal and an unmodulated clock signal, where both clock signals are substantially synchronized and where the ASIC architecture minimizes the number of external pins and silicon area needed to provide the dual clock signals.
One aspect of the present invention provides a clock tree configuration for an integrated circuit, such as an application specific integrated circuit (ASIC), that includes: (a) a clock signal input trunk path for receiving an externally generated clock signal, which may be a pure clock signal; (b) a conditioning module operatively coupled to the input trunk path for receiving the externally generated clock signal and for generating a spread spectrum clock signal at a first output thereof; (c) a first branch path extending from the first output of the conditioning module for carrying the spread spectrum clock signal to at least a first section of the integrated circuit; and (d) a second branch path extending from one of (i) the input trunk path and (ii) the conditioning module, for carrying the externally generated clock signal to at least a second section of the integrated circuit. The conditioning module may include a second output to which the externally generated signal is passed, such that the second branch path extends from the second output of the conditioning module. Alternatively, the second branch path may extend directly from the input trunk. Preferably, the input trunk path includes the only clock signal input for the integrated circuit, thereby reducing the number of pin-outs (i.e. external pins) and silicon area necessary for the integrated circuit. Additionally, because the clock signals on both branch paths are derived from the same externally generated clock signal, the clock signals on both branch paths will be substantially synchronized, thereby reducing drift, skew or delay errors in the clock I/O buffers, between the various sections of the integrated circuit and/or between the various components coupled to, or part of the electronic device in which the integrated circuit is a part.
Another aspect of the present invention provides a clock signal circuit arrangement that includes: (a) a clock signal generator for generating a substantially stable clock signal; and (b) an integrated circuit, such as an ASIC, having a clock tree including: (i) an input trunk operatively coupled to the clock signal generator for receiving the substantially stable clock signal; (ii) a conditioning circuit operatively coupled to the input trunk path for receiving the substantially stable clock signal and for generating a spread spectrum clock signal at a first output thereof; (iii) a first branch path extending from the first output of the conditioning circuit for carrying the spread spectrum clock signal to at least a first section of the integrated circuit; and (iv) a second branch path extending from one of the input trunk and the conditioning circuit for carrying the externally generated clock signal to at least a second section of the integrated circuit. The conditioning circuit may include a second output to which the externally generated signal is passed, such that the second branch path extends from the second output of the conditioning circuit. Alternatively, the second branch path may extend directly from the input trunk. Preferably, the input trunk path includes the only clock signal input for the integrated circuit, thereby reducing the number of pin-outs (i.e. external pins) and silicon area necessary for the integrated circuit. Additionally, because the clock signals on both branch paths are derived from the same externally generated clock signal, the clock signals on both branch paths will be substantially synchronized, thereby reducing drift, skew or delay errors in the clock I/O buffers, between the various sections of the integrated circuit and/or between the various components coupled to, or part of the electronic device in which the integrated circuit is a part.
Another aspect of the present invention provides a method for reducing EMI emissions of an ASIC device while maintaining a suitable timing scheme within the ASIC device. This method includes the steps of: (a) receiving a substantially stable clock signal input trunk of the ASIC device; (b) embedding an SSCG within the ASIC device on a path to receive the substantially stable clock signal from the input trunk; (c) generating a spread spectrum clock signal at an output of the SSCG module; (d) directing the spread spectrum clock signal along a first clock signal branch of the ASIC device to at least a first section of the ASIC device; (e) providing a second clock signal branch within the ASIC device along a path to receive the substantially stable clock signal; and (f) directing the substantially stable clock signal along the second clock signal branch to at least a second section of the ASIC device.